The present invention generally relates to semiconductor devices having detecting circuits for detecting states of fuses in fuse circuits, and more particularly to a semiconductor device having a fuse circuit provided with pairs of fuses and a detecting circuit for detecting states of each pair of fuses in the fuse circuit.
Fuses which are blown by electrical or laser programming are often used in semiconductor devices. For example, fuses are used in a semiconductor memory device employing a redundancy configuration, so that redundancy memory cells may be used in place of defective memory cells. In addition, fuses are often used to select one or a plurality of circuit elements such as resistors provided in a semiconductor device.
In the case of the semiconductor memory device such as a random access memory (RAM), a large number of memory cells are arranged along rows and columns. The density of defects generated in the memory device in the manufacturing process is relatively independent of the integration density of the memory device and is dependent on the manufacturing technology. In general, the higher the integration density of the memory device, the greater the ratio of normal memory cells to defective memory cells. This is one of the advantages of increasing the integration density of the memory device.
However, when the memory device includes defective memory cells, the memory device will not operate correctly and must therefore be destroyed. As a result, despite the low ratio of defective memory cells to the normal memory cells, the manufacturing yield of the memory device is reduced. In order to overcome this problem of defective memory cells, the memory device employs the redundancy configuration. According to the redundancy configuration, one or two rows or columns of redundancy memory cells are provided, and a row or column of redundancy memory cells is selected instead of a defective row or column of memory cells when a defective memory cell is detected in the defective row or column. A redundancy control circuit is provided to store address information of such a defective row or column of memory cells and to disable regular decoders for selecting normal memory cells, so as to select the row or column of redundancy memory cells in response to an address of the defective row or column. The redundancy control circuit comprises fuse-type read only memories (ROMs) each having an information storing circuit.
A unit information storing circuit in a prior art device incorporates one fuse for each bit of the address information to be stored. Therefore, the information storing circuit stores a datum "1" or "0" by a blown or unblown fuse. For example, when writing the datum "1", a polysilicon fuse is blown by electrical or laser programming. However, especially when the polysilicon fuse is blown by the electrical programming, the polysilicon fuse may grow back during the life of the memory device. For this reason, when only one fuse is provided for one bit of the address information and the grow back occurs, it is impossible to make use of the redundancy memory cells and the reliability of the memory device is unsatisfactory.
Accordingly, an improved memory device was previously proposed in a U.S. Pat. No. 4,592,025 in which the assignee is the same as the assignee of the present application. According to this previously proposed memory device, two fuses are provided for one bit of the address information. For example, when writing the datum "1", both of the two fuses are blown by electrical or laser programming. A detection to determine the states of the fuses may be carried out by obtaining a logical sum of signals obtained via the two fuses. From the logical sum, it is possible to detect whether the two fuses are both unblown or at least one of the two fuses is blown. Hence, in the above case, even when the two fuses are blown by the electrical programming but one of the fuses grows back, it is still possible to detect that the bit of the address information is intended to contain the datum "1". As a result, the reliability of the memory device is greatly improved compared to the prior art device in which only one fuse is provided for one bit of the address information, because the probability that both the two blown fuses will grow back is considerably small compared to the probability that the single fuse will grow back.
But in actual practice, the fuses need to be re-programmed if the fuses which should be blown are actually unblown due to incomplete programming or grow back. It is easy to detect the state of the fuse when only one fuse is provided for one bit of the address information. However, when two fuses are provided for one bit of the address information, it is impossible to know from the logical sum described above whether only one of the two fuses is blown or both the two fuses are blown. Furthermore, in the case where only one of the two fuses is blown, it is impossible to discriminate which one of the two fuses is blown.
When two fuses are provided for one bit of the address information but one of the two fuses which should be blown is actually unblown, the situation is the same as the prior art device described before. In other words, when the blown fuse grows back, there is a problem in that it is impossible to make use of the redundancy memory cells and the reliability of the memory device is unsatisfactory. Hence, in this case, it is desirable to discriminate which one of the two fuses is unblown and re-program the unblown fuse so that both the two fuses are blown as originally intended.